Author, Subjects, Keywords

Cited Author

 
 
   » By Author or Editor
 » Browse Author by Alphabet
 » By Journal
 » By Subjects
 » By Affiliations
 » By Type
 » By Year
 » By Latest Additions
 
 
   » By Author
 » Top 20 Authors
 » Top 20 Article
 » Top 20 Journal Cited
 » Top 20 Cited
 » Top 20 Author Cited
 » Usage Since Sept 2007


 
 
 

Login | Create Account

A VHDL Implementation of UART Design with BIST Capability

Mohd. Yamani Idna, and Mashkuri Yaacob, and Zaidi Razak, (2006) A VHDL Implementation of UART Design with BIST Capability. Malaysian Journal of Computer Science, 19 (1). pp. 73-86. ISSN 0127-9084

Full text not available from this repository.

Official URL: http://mjcs.fsktm.um.edu.my/detail.asp?AID=353

Affiliations

University of Malaya, Faculty of Computer Science & Information Technology

Abstract

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years. Design engineers who do not design systems with full testability in mind open themselves to the increased possibility of product failures and missed market opportunities. BIST is a design technique that allows a circuit to test itself. In this paper, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.

Item Type:Journal
Keywords:Built-In-Self-Test (BIST), UART, simulation, synthesis
Subjects:Q Science
ID Code:352

S. Wang, “Generation of low power dissipation and high fault coverage patterns for scan-based BIST”, in Proceedings of International Test Conference, 2002, pp. 834 –843.

M. Ibrahim Abubakar, “A Built in Self Testable Bit-Slice Processor”, Faculty of Computer Science & Information Technology, University of Malaya, May 1995.

J. Turino, “RTL DFT Rule Checking – The Circuit Designer’s Secret Weapon”, Integrated System Design Magazine, 2000.

A. P. Stroele, and H. J. Wunderlich, “Hardware-Optimal Test Register Insertion”, in IEEE Transactions On Computer-aided Design of Integrated Circuits and Systems, June 1998, Vol. 17, No. 6, pp. 531-539.

Z. Navabi, “VHDL Analysis and Modeling of Digital Systems”, McGraw-Hill Inc., 1991.

M. S. Michael, “A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs”, National Semiconductor Application Note 493, April 1989.

“PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs”, National Semiconductor Application Note, June 1995.

M. S. Harvey, Generic UART Manual, SiliconValley, December 1999.

O. A. Petlin, and S. B. Furber, "Built-In-Self-Testing of Micropipelines” in Advanced Research in Asynchronous Circuits and Systems, IEEE, 1997, pp 22-29.

J. Turino, “RTL DFT Rule Checking – The Circuit Designer’s Secret Weapon”, Integrated System Design Magazine, 2000.

C. H. Roth, Digital System Design Using VHDL, PWS Publishing Company, 1998. http://www.xess.com

Repository Staff Only: item control page
 
 
 
 
 
   
© Copyright 2007 MyAIS Faculty of Computer Science and Information Technology, University of Malaya – All Rights Reserved. Malaysian Abstracting and Indexing System is powered by EPrints 3 which is developed by the School of Electronics and Computer Science at the University of Southampton. More information and software credits.