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Pencirian Proses Penyediaan Titanium Silisida untuk Kegunaan Saling Hubung Litar Bersepadu CMOS

Uda Hashim, and Burhanuddin Yeop Majlis, and Sahbudin Shaari, (2000) Pencirian Proses Penyediaan Titanium Silisida untuk Kegunaan Saling Hubung Litar Bersepadu CMOS. Jurnal Kejuruteraan (12). pp. 31-43. ISSN 0128-0198

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Affiliations

MIMOS Berhad, Pusat Teknologi Semikonduktor
Universiti Kebangsaan Malaysia. Pusat Penyelidikan Mikroelektronik UKM-TM

Abstract

Characterization of the titanium silicide process preparation for the application of interconnection in CMOS integrated circuit has been characterized. The process characterize are titanium deposition, selective wet etching, native oxide removal and thermal budget adjustment of reflow- anneal borophosphosilicate glass. Titanium film was sputter-deposited at various times by PVD system. The relationship between titanium deposition time and film thickness is plotted. The relation Y = 3.8X0.89 which was generated by the graph is employed to determine deposition time at any specific thickness. The solution which is the mixture of NH4OH, 30% H2O2, H2O (1:1:5) for solution 1, H2SO4 10% HF, H2O (30:1:69) for solution 2, and H2SO4 30% H2O2 (1: 1) for solution 3 have been tested for titanium selectivity wet etching. Base on the calculation, the etching rate of the solution 1, 2, and 3 are 0.15 nm/s, 7.8 nm/s and 1.16 nm/s, respectively. The wafer, which is dipped in the HF solution before titanium deposition revealing a better silicide/silicon, interface after heat treatment process. The reduction thermal budget of BPSG reflow-anneal from 900°C to 850°C for 30 minutes using furnace couple with additional anneal at 950°C for 60 seconds rapid 60 seconds rapid thermal annealer revealed the same surface topography with the wafer that annealed at 900°C for 30 minutes using conventional furnace.

Pencirian proses penyedian TiSi${\tiny{2}}$ untuk kegunaan dalam saling hubung litar bersepadu CMOS telah dilakukan. Proses yang telah dicirikan ialah pemendapan logam titanium, punaran basah logam titanium, penyingkiran oksida asli dan peruntukan terma proses alir-semula gelas silikat terdop boron dan fosforan. Logam titanium telah dimendap dengan menggunakan pemendap wap fizikal (PVD) pada lima tempoh yang berbeza. Graf ketebalan logam dan tempoh pemendapan logam titanium dilakarkan. Persamaan Y = 3. 8X° yang dijanakan oleh graf digunakan untuk menentukan tempoh pemendapan bagi ketebalan logam titanium yang dikehendaki. Tiga larutan telah dipilih untuk menentukan kadar punaran dan punaran memilih iaitu larutan 1 yang merupakan campuran NH${\tiny{2}}$OH, 30% H${\tiny{2}}$O${\tiny{2}}$ H${\tiny{2}}$0${\tiny{2}}$' (1:1:5), larutan 2 ialah campuran H${\tiny{2}}$S0${\tiny{4}}$' 10% HF, H${\tiny{2}}$0 (30:1:69), manakala larutan 3 pula ialah campuran H${\tiny{2}}$S0${\tiny{4}}$, 30% H${\tiny{2}}$O${\tiny{2}}$ (1:1). Bersandarkan kepada pengiraan, kadar punaran basah bagi ketiga-tiga larutan 1, 2 dan 3 ialah masing-masingnya 0.15 nm/saat, 7.8262 nm/saat dan 1.16 nm/saat. Wafer yang dicelup ke dalam larutan HF sebelum pemendapan logam titanium menghasilkan antaramuka silisida/silikon yang lebih rata dan bersih selepas proses rawatan haba. Peruntukan terma proses alir-semula gelas silikat terdop boron dan fosforan yang dikurangkan dan 900°C ke 850°C selama 30 minit dan ditambah dengan satu rawatan haba cepat pada suhu 950°C selama 60 saat oleh RTA menunjukkan topografi permukaan BPSG yang hampir rata dengan topografi permukaan BPSG yang dirawat pada suhu 900°C selama 30 minit.

Item Type:Journal
Keywords:Titanium silicon
Subjects:Q Science, Computer Science
T Technology, Engineering
ID Code:4138

Morgan A.E., Broadbent E.K., Delfino M., Coulman B. & Sadana D.K. 1987. Characterization of a self-aligned cobalt Silicide process. J. Electrochem. Soc.: Solid State Science and Technology.

Ting C.Y., Wittmer M., Iyer S. S. & Brodsky S. B. 1984. Interaction between Ti and Si02. J. Electrochem. Soc.: Solid State Science and Technology.

Scott D.B. 1987. Titanium Disilicide contact resistivity and its impact on 1-um CMOS circuit performance. IEEE Transactions on Electron Devices 34(3): 562-573.

Schroder D.K. 1990. Semiconductor Material and Device Characterization. New York: John Wiley and Sons Inc.

Levy D., Delpech P. & Paoli M. 1990. Optimization of a self-aligned titanium Silicide process for submicron technology. IEEE Transactions on Semiconductor Manufacturing 3(4).

Yang E.S. 1990. Microelectronics Devices. Singapore:, McGraw-Hill Book Company.

K. Maex. 1993. Silicides for integrated circuits: TiSi2 and CoSi2. Materials Science and Engineering 53-153.

Wolf S. 1986. Silicon Processing for The VLSI Era in Process Integration. New York: Lattice Press.

Tabasky M., Bulat ES., Ditchek B.M., Sullivan M.A. & Shatas S.C. 1987. Direct silisidation of Co on Si by Rapid Thermal Annealing. IEEE Transactions on Electron Devices 34(3).

Muller & Kamis. 1977. Device Electronics for Integrated Circuits. New York:, John Wiley and Sons Inc.

Levy S.B. 1989. Microelectronic Materials and processes. The Netherlands: Klauwer Academic Publisher.

Jreger R.C. 1990. lntroduction to Microelectronic Fabrication. New York:, John Wiley & Son.

Campbell S.A. 1996. The Science and engineering of Microelectronics Fabrication. Oxford:, Oxford University Press.

Wilson S.R. & C. J. Tracy. 1993. Handbook of Multilevel Metallization for Integrated Circuits, Materials, technology and Application. New Jersey:, Noyes Publications.

Mogami T., Wakabayashi H., Saito Y., Tatsumi T., Matsuki T. & Kunio T. 1996. Low-Resistance Self Aligned Ti-Silicide Technology for sub-Quarter Micron CMOS Devices. IEEE Transactions on Electron Device 43(6).

Hook T.B., Mann R.W. & Nowak E.J. 1995. Titanium Silicide/Silicon Nonohmic contact resistance for NFET, PFET, diffused Resistors and NPN in a BiCMOS Technology. IEEE Transactions on Electron device 42(4).

Brat T. & Osburn CM. 1996. Self-Aligned Ti Silicide Formed by Rapid Thermal Annealing. J. Electrochem. Soc.: Solid State Science and Technology.

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